AD9874EB datasheet(18/40 Pages) AD

18 / 40 page

REV. 0

–18–

AD9874

CLKOUT

RSCLK

SCK

SEL

MOSI

DOUTB

MISO

RFS

DOUTA

SPI

SSI

ADSP-2153X

SERIAL

PORT

SPI-PORT

Figure 4b. Example of AD9874 and ADSP-2153x Interface

As shown in Figure 4b, AD9874’s synchronous serial interface

(SSI) links the receive data stream to the DSP’s Serial Port (SPORT).

For AD9874 set-up and register programming, the device connects

directly to ADSP-2153x’s SPI-PORT. Dedicated select lines (SEL)

allow the ADSP-2153x to program and read back registers of

multiple devices using only one SPI port. The DSP driver code

pertaining to this interface is available on the AD9874 web page

(http://products.analog.com/products/info.asp?product=AD9874).

POWER CONTROL

To allow power consumption to be minimized, the AD9874

possesses numerous SPI-programmable power-down and bias

control bits. The AD9874 powers up with all of its functional

blocks placed into a standby state (i.e., STBY Register default is

0xFF). Each major block may then be powered up by writing a 0

to the appropriate bit of the STBY Register. This scheme provides

the greatest flexibility for configuring the IC to a specific appli-

cation as well as for tailoring the IC’s power-down and wake-up

characteristics. Table VI summarizes the function of each of the

STBY bits. Note, when all the blocks are in standby, the master

reference circuit is also put into standby and thus the current is

reduced by a further 0.4 mA.

Table VI. Standby Control Bits

Current

STBY

Reduction Wake-Up

Bit

Effect

(mA)

Time (ms)

7:REF

Voltage Reference OFF;

0.6

<0.1 (CREF

all biasing shut down.

= 4.7 nF)

6:LO

LO Synthesizer OFF,

1.2

Note 2

IOUTL three-state.

5:CKO

Clock Oscillator OFF

1.1

Note 2

4:CK

Clock Synthesizer OFF,

1.3

Note 2

IOUTC three-state. Clock

buffer OFF if ADC is OFF.

3:GC

Gain Control DAC OFF.

0.2

Depends

GCP and GCN three-state.

on CGC

2:LNAMX LNA and Mixer OFF. CXVM,

8.2

<2.2

CXVL, and CXIF three-state.

1:Unused

0:ADC

ADC OFF; Clock Buffer OFF

9.2

<0.1

if CLK synthesizer OFF; VCM

three-state; Clock to the digital

filter halted; Digital outputs

static.

NOTES

1When all blocks are in standby, the master reference circuit is also put into

standby and thus the current is reduced by a further 0.4 mA.

2Wake-up time is dependent on programming and/or external components.

The AD9874 also allows control over the bias current in the LNA,

mixer, and clock oscillator. The effects on current consumption

and system performance are described in the section dealing

with the affected block.

LO Synthesizer

The LO Synthesizer shown in Figure 5 is a fully programmable

PLL capable of 6.25 kHz resolution at input frequencies up to

300 MHz and reference clocks of up to 25 MHz. It consists of a

low noise digital phase-frequency detector (PFD), a variable

output current charge pump (CP), a 14-bit reference divider,

programmable A and B counters, and a dual-modulus 8/9 prescaler.

The A (3-bit) and B (13-bit) counters, in conjunction with the

dual 8/9 modulus prescaler, implement an N divider with N =

B + A. In addition, the 14-bit reference counter (R Counter)

allows selectable input reference frequencies, fREF, at the PFD

input. A complete PLL (phase-locked loop) can be implemented

if the synthesizer is used with an external loop filter and VCO

(voltage controlled oscillator).

The A, B, and R counters can be programmed via the following

registers: LOA, LOB, and LOR. The charge pump output current

is programmable via the LOI Register from 0.625 mA to 5.0 mA

using the following equation:

IPUMP

LOI

=+ ×

()

10 625

(2)

An on-chip fast acquire function (enabled by the LOF bit)

automatically increases the output current for faster settling

during channel changes. The synthesizer may also be disabled

using the LO standby bit located in the STBY Register.

FAST

ACQUIRE

8/9

A, B

COUNTERS

BUFFER

LOA, LOB

FROM

VCO

REF

BUFFER

REF

LOR

REF

PHASE/

FREQUENCY

DETECTOR

TO EXTERNAL

LOOP

FILTER

CHARGE

PUMP

Figure 5. LO Synthesizer

The LO (and CLK) synthesizer works in the following manner.

The externally supplied reference frequency, fREF, is buffered and

divided by the value held in the R counter. The internal fREF is

then compared to a divided version of the VCO frequency, fLO.

The phase/frequency detector provides UP and DOWN pulses

whose widths vary depending upon the difference in phase and

frequency of its two input signals. The UP/DOWN pulses con-

trol the charge pump making current available to charge the

external low-pass loop filter when there is a discrepancy between

the inputs of the PFD. The output of the low-pass filter feeds an

external VCO whose output frequency, fLO, is driven such that

its divided down version, fLO, matches that of fREF, thus closing

the feedback loop.

The synthesized frequency is related to the reference frequency

and the LO Register contents as follows:

LOB

LOA

LOR

REF

=×

() /

(3)

Note, the minimum allowable value in the LOB Register is 3 and

its value must always be greater than that loaded into LOA.

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