Hardware design

SPBTLE-1S

16/27

DocID030445 Rev 3

5

Hardware design



All unused pins should be left floating; do not ground



GND pin must be well grounded



Traces should not be routed underneath the module

The area around the module should be free of any ground planes, power planes,

trace routings, or metal for 6 mm from the module antenna position, in all

directions.

5.1

Reset circuitry

The SPBTLE-1S module requires an external pull-up reset circuitry to ensure proper

operation at power on. Refer to the “Reset management” chapter of the BlueNRG-1

datasheet for details.

Figure 10: Reset circuitry

5.2

Debug interface

The SPBTLE-1S embeds the ARM serial wire debug (SWD) port. It is two pins (clock and

single bi-directional data) debug interface, providing all the debug functionality plus real

time access to system memory without halting the processor or requiring any target

resident code.

Table 7: Debug interface pin

Pin functionality

Module PIN

Pin description

SWCLK

12

SWD clock signal

SWDIO

13

SWD data signal

For more information refer to the BlueNRG-1 technical documentation