SLG46200 datasheet(21/69 Pages) DIALOG

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000-0046200-124

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SLG46200

9.0 Pulse Width Modulator (PWM)

The SLG46200 contains a 2-input Pulse Width Modulator with an 8-bit resolution and 7.8MHz clocking speed. The PWM has a

4:1 mux for IN1 selection, an 8-bit Comparator, a Mode Select option and a Dead Band Control function.

9.1 PWM Input Modes

IN1 for the PWM is an 8-bit data string that can be selected from one of four sources; the ADC Output, the S2P <15:8>, the Finite

State Machine (through the Counter/Delay logic cells) or the source IN- of the DCMP1 logic cell. Reg <408:407> is used as a

2-bit selection input to the 4:1 mux with the previously mentioned 8-bit data strings.

IN2’s 8-bit data string is sourced from the Counter/Delay logic cell in the SLG46200 device.

The 8-bit PWM has two control signals; a SET bit and a Power Down signal. Both of these signals come from the SLG46200’s

Connection Matrix.

•

If SET = “1” then PWM IN1 = “255”, otherwise PWM normal operation

•

If PWR DOWN = “1” then PWM is “off”, otherwise PWM is “on”

9.2 PWM Output Mode Selection

The output (OUT+) duty cycle can be set to either 0% to 99.6% or 0.39% to 100%. When both inputs are equal the output signal

(EQ) will go high.

9.3 PWM Functional Diagram

Figure 5. PWM Functional Diagram

8-bit comparator

IN1

IN2

ADC<7:0>

From DCMP1 IN-

S2P <15:8>

FSM0(Q<7:0>)

OUT

From Connection Matrix output <1>

reg <408:407>

Q4PWM<7:0>

(8 bits ramp data from CNT1/DLY1)

From Connection Matrix output <2>

PWR DOWN

SET

CLK4PWM

To Connection Matrix input <29>

Mode

Select

3-bit delay

dead band

control

reg <413>

reg <411:409>

To Connection Matrix input <22>

To Connection Matrix input <28>

To Connection Matrix input <27>

OUT+

OUT-

OUT

S2P <7:0>

reg <382:375>

reg <390:383>

reg <398:391>

reg <404:403>

Connection Matrix

output <11:10>

reg <318>

<1:0>

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