VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC8113

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

Page 2

© VITESSE SEMICONDUCTOR CORPORATION

G52154-0, Rev 4.2

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

3/19/99

CRU clock and data signals. (In this mode the VSC8113 operates just like the VSC8111). The receive section

also contains a SONET/SDH frame detector circuit which is used to provide frame pluses during the A1, A2

boundary in the serial to parallel converter. This only occurs when OOF is high. Both internal and external LOS

functions are supported.

VSC8113 Block Diagram

DQ

0

1

0

1

D

Q

0

1

0

1

8

RXOUT[7:0]

RXLSCKOUT

FP

OOF

EQULOOP

TXDATAOUT+/-

TXCLKOUT+/-

8

TXIN[7:0]

TXLSCKOUT

TXLSCKIN

0

1

FACLOOP

LOOPTIM0

REFCLK

LOOPTIM1

CMU

Divide-by-8

1:8

DEMUX

FRAMER

Divide-by-8

8:1

MUX

0

1

DQ

QD

Divide-by-3/12

RX50MCK

EQULOOP

CRU

RXCLKIN+/-

DSBLCRU

0

1

0

1

1

0

CRULOCKDET

LOSOUT

CMULOCKDET

losdet

REFCLKP+/-

LOSTTL

LOSPECL

LOSDETEN_

REC-DATA

REC-CLK

0

1

0

1

CRUREFCLK

CRUREFSEL

cmurefclk

RXDATAIN+/-

CRUEQLP