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SL28PCIe10ALC データシート(PDF) 2 Page - Silicon Laboratories |
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SL28PCIe10ALC データシート(HTML) 2 Page - Silicon Laboratories |
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2 / 16 page ![]() SL28PCIe10 .......................................Document #: Rev 1.1 Page 2 of 16 32-QFN Pin Definitions Programmable Single ended clock SL28PCIe10 allows flexibility of programming any frequency at single ended output Prog_SE. Prog_SE can be factory programmed to any frequency as required by the end user with a 3.3V swing single ended output. This clock can have a feature of Spread Spectrum to reduce EMI. Pin No. Name Type Description 1 VDD PWR 3.3V Power supply 2 VSS GND Ground 3 NC NC No Connect. 4 NC NC No Connect. 5 VDD_27 PWR 3.3V Power supply 6 27M_NSS O,SE Non-spread 27MHz video clock output 7 Prog_SE O, SE Spreadable Programmable Single-Ended clock output 8 VSS_27 GND Ground 9 VSS_SRC GND Ground 10 SRC0 O, DIF 100MHz True differential serial reference clock 11 SRC0# O, DIF 100MHz Complement differential serial reference clock 12 VSS_SRC GND Ground 13 SRC1 O, DIF 100MHz True differential serial reference clock 14 SRC1# O, DIF 100MHz Complement differential serial reference clock 15 VDD_SRC_IO PWR Scalable 3.3V to 1.05V power supply for output buffer 16 OE#_SRC2_SRC3 I 3.3V tolerance input to disable Output on Pin 7 and Pin 8 17 VDD_SRC PWR 3.3V Power supply 18 VDD_SRC_IO PWR Scalable 3.3V to 1.05V power supply for output buffer 19 SRC2# O, DIF 100MHz True differential serial reference clock 20 SRC2 O, DIF 100MHz Complement differential serial reference clock 21 VSS_SRC GND Ground 22 SRC3# O, DIF 100MHz True differential serial reference clock 23 SRC3 O, DIF 100MHz Complement differential serial reference clock 24 VDD_SRC PWR 3.3V Power supply 25 CK_PWRGD/PD# I 3.3V LVTTL input. After CK_PWRGD (active HIGH) assertion, this pin becomes a real-time input for asserting power down (active LOW) 26 VSS_REF GND Ground 27 XOUT O, SE 25MHz Crystal output 28 XIN I 25MHz Crystal input 29 VDD_REF PWR 3.3V Power supply for outputs and also maintains SMBUS registers during power-down 30 REF PD, I/O Reference 25MHz clock output 31 SDATA I/O SMBus compatible SDATA 32 SCLK I SMBus compatible SCLOCK |
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