4

®

ISO808

SYMBOL

DESCRIPTION

MIN

TYP MAX UNITS

Convert Pulse Width

40

4500

ns

BUSY Delay

120

ns

BUSY LOW

8

µs

BUSY Delay after

220

ns

End of Conversion

Aperture Delay

40

ns

Conversion Time

5.7

8

µs

Acquisition Time

2

µs

Throughput Time

9

10

µs

R/C LOW to DATACLK Delay

450

ns

DATACLK Period

440

ns

Data Valid to DATACLK

20

75

ns

HIGH Delay

Data Valid after

100

125

ns

DATACLK LOW Delay

DIGITAL

PIN #

NAME

I/O

DESCRIPTION

1

RC

I

Read/Convert. With BUSY high, a falling edge on R/C initiates a new conversion.

2

BUSY

O

At the start of conversion BUSY goes LOW and stays LOW until conversion is complete.

3

Isolated Digital Supply Volts.

10

Digital Supply Volts.

11

Analog Supply Volts.

12

Analog Input.

13

Analog Input.

14

Analog Input.

15

CAP

Reference Buffer Output. 2.2

µF tantalum capacitor to ground.

16

REF

Reference Input/Output. 2.2

µF tantalum capacitor to ground.

17

AGND

Analog Ground.

18

SB/BTC

I

Selects Straight Binary or Binary Two’s Complement for output data format.

19

DGND1

Digital Ground.

26

DGND2

Isolated Ground.

27

DATACLK

O

Data Clock Output.

28

SDATA

O

Serial Output Synchronized to DATACLK.

TABLE I. Pin Assignments.

PIN CONFIGURATION

ANALOG

INPUT

VIA 200

Ω

VIA 100

Ω

RANGE

TO

TO

TO

IMPEDANCE

±10V

AGND

CAP

22.9k

Ω

±5V

AGND

CAP

13.3k

Ω

±3.33

CAP

10.7k

Ω

0V to 10V

AGND

AGND

13.3k

Ω

0V to 5V

AGND

AGND

10.0k

Ω

0V to 4V

AGND

10.7k

Ω

TABLE I. Input Range Connections. See Figure 3 for

complete information.

SDATA

DATACLK

DGND2

DGND1

SB/BTC

AGND

REF

CAP

R/C

BUSY

+5V

DIG2

+5V

DIG1

+5V

ANA

R1

IN

R2

IN

R3

IN

1

2

3

10

11

12

13

14

28

27

26

19

18

17

16

15

ISO808