RFHCS362G datasheet(35/60 Pages) MICROCHIP

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Preliminary

DS41189A-page 35

rfHCS362G/362F

6.7

Mode Control Logic

The mode control logic pin RFENIN controls the oper-

ation of the transmitter (Table 6-7). When RFENIN

goes high, the crystal oscillator starts up. The voltage

on the LF pin ramps up proportionally to the RF fre-

quency. The PLL can lock onto the frequency faster

than the starting up crystal can stabilize. When the LF

pin reaches 0.8V, the RF frequency is close to locked

on the crystal frequency. This initiates a 150 micro-

second delay to ensure that the PLL settles. After the

delay, the PS/DATAASK bias current and power ampli-

fier are enabled to start transmitting.

When RFENIN goes low, the transmitter goes into low

power Standby mode. The power amplifier is dis-

abled, the crystal oscillator stops, and the PS/

DATAASK pin is driven low. This will be a conflict if other

circuitry drives the PS/DATAASK pin high while RFENIN

is low. The encoder DATA pin is typically the only con-

nection to PS/DATAASK and it always drives DATA low

before RFENOUT goes low.

For most applications the RFENIN pin is connected

directly to the RFENOUT pin. The RFENIN pin has an

internal pull-down resistor.

TABLE 6-7:

RFENIN PIN STATES

RFEN

Description

Transmitter and CLKOUT in Standby

Transmitter and CLKOUT enabled

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