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S29AL016D データシート(PDF) 21 Page - SPANSION |
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S29AL016D データシート(HTML) 21 Page - SPANSION |
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21 / 58 page ![]() December 17, 2004 S29AL016D_00_A2 S29AL016D 21 Pre l i m i n a r y Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up. |
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