Document Number: 002-01122 Rev.*L

Page 53 of 59

S29AS016J

19. Erase and Programming Performance

Notes

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program

times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table on page 32 for further information on

command definitions.

6. The device has a minimum erase and program cycle endurance of 100,000 cycles per sector.

20. Package Pin Capacitance

Notes

1. Sampled, not 100% tested.

Parameter

Typ (Note 1)

Max (Note 2)

Unit

Comments

Sector Erase Time

0.5

10

s

Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time

19.5

s

Byte Programming Time

6

µs

Excludes system level

overhead (Note 5)

Word Programming Time

6

150

µs

Chip Programming Time

(Note 3)

Byte Mode

20

160

s

Word Mode

14

120

s

Parameter Symbol

Parameter Description

Test Setup

Package

Typ

Max

Unit

Input Capacitance

TSOP

4.0

6.0

pF

BGA

4.2

5.0

Output Capacitance

TSOP

4.5

5.5

BGA

5.4

6.5

Control Pin Capacitance

TSOP

5

6.5

BGA

3.9

4.7

WP# Pin Capacitance

TSOP

8.5

10.0

BGA

8.5

10.0