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TVS Diode Arrays

SPUSB1 Series

Upstream USB Port Terminator with ESD Suppression & EMI Filtering

Absolute Maximum Ratings

Supply Voltage V

Parameter

Rating

Unit

BUS

DC Power per Resistor

Package Power

Temperature Range:

Operating

Storage

5.5

100

200

-40 to +85

-65 to +150

V

mW

mW

C

°

Resistance R1 (SPUSB1AJT only)

Parameter

Unit

Ω

Ω

Ω

Specifications

(at 25°C unless specified otherwise)

Resistance R1 (SPUSB1CJT only)

Resistance R1 (SPUSB1BJT only)

Resistance R2

Capacitance C1 @ 2.5 v DC, 1MHz

Diode Leakage at 3.3V

Diode Reverse Bias Stand-off Voltage, 1= 10µA

Signal Clamp Voltage:

Positive Clamp, 10mA

Negative Clamp, 10mA

In-system ESD Withstand Voltage

Human Body Model (MIL-STD-883D, method 3015

IEC 81000-4-2, contact discharge method (I/O pins)

IEC 81000-4-2, contact discharge method (V

pin)

(1)

BUS

Clamping Voltage During ESD Discharge

MIL-STD-883D (Method 3015), 8kV

(1)

MAX

TYP

MIN

kΩ

pF

nA

V

12

33

22

1.5

47

1

6%

26%

18%

1.2%

38%

5.5

14%

40%

26%

18%

56%

100

Positive

Negative

5.6

-1.2

6.8

-0.8

8.0

-0.4

V

V

±30

±15

±25

kV

kV

kV

V

V

10

-5

Note:

(1) ESD applied to input/outputV

pins with respect to GND, one at a time.

Clamping Voltage is measured at the opposite side of the EMI filter to the ESD pin (ie: if ESD is applied to pin1 then clamping

voltage is measured at pin 6). Unused pins are open.

These parameters guaranteed by design.

DD

Standard

2

C1

GND

D1

D2

D3

D4

1

3

C1

5

6

4

R2

3.3V

R1

R1

VBUS

D+

USB 1.1

CONNECTOR

D-

D+

USB 1.1

CONTROLLER

IC

D-

GND

2

C1

GND

D1

D2

D3

D4

1

3

C1

5

6

4

R2

3.3V

R1

R1

VBUS

D-

USB 1.1

CONNECTOR

D+

D-

USB 1.1

CONTROLLER

IC

D+

GND

Figure 1. Full-Speed Devices (12Mbits per second)

For full speed operation the pull-up resistor R2 is connected to the D+ pin.

Figure 2. Low-Speed Devices (1.5Mbits per second)

Low speed connection requires the pull-up resistor R2 to be connected to the D-

pin. Please note the reversal of the D- and D+ pins on Figure 2 versus Figure 1.

APPLICATIONS INFORMATION