LP6303-01

Apr.-2014

www.lowpowersemi.com

Page 10 of 11

Preliminary Datasheet

LP6303

PCB Layout

Layout is very critical for PMIC designs. For LP6303 PCB layout considerations, please refer to the following

suggestions to get best performance.



It is suggested to use 4-layer PCB layout and place LX plane and output plane on the top layer, place VIN

plane in the inner layer.



The top layer SMD input and output capacitors ground plane should be connected to the internal ground layer

and bottom ground plane individually by using vias.



The GND should be connected to inner ground layer directly by using via.



High current path traces need to be widened.



Place the input capacitors as close as possible to the VINx pin to reduce noise interference.



node. Complete the layout by using short and wide traces.



The top layer exposed pad ground plane should be connected to the internal ground layer and bottom ground

plane by using a number of vias to improve thermal performance.



Place the input capacitors as close as possible to the VINx pin to reduce noise interference.