Functional Description

externally connected. As soon as an internal switching threshold of 7 V is reached, trigger pulses are delivered at

the output TR with a repetition instalment of 960 µs. After successful triggering of the oscillator circuit, an

oscillation detector guarantees blocking of further trigger pulses. It identifies a stable oscillating process, after a

minimum of oscillations is detected per timing.

As soon as a switching threshold of 8 V is reached, all logic units are reset and the timer output S is activated as

well. The IC starts a counter, which interrups the control after one second.

Furthermore, the IC monitors the temperature and the oscillation circuit from a supply voltage of 8 V.

The comparator input EI is useful for error detection. Voltage > 3.75 V, applied at EI, are evaluated as error

signals. The error signal is enqired and registered within a cycle repeating every 960 µs. After registration of the

error signal, a counter starts to generate a delay of one second. After this delay time, the voltage at EI is evaluated

again.

The error storage is set only after a second error, appearing within a directly following evaluation cycle. This error

storage is resettable by a short-time power supply disconnection, or with input LW connected via a change of

lamp.

The error storing causes the cutting further triggers and the control of the turn-off transistor as well, which turns

the output TR to ground. Therefore, the turn-off transistor prevents the control of the oscillator circuit, attenuating it

extremly quickly.

Thereby, the current consumption increases by the control of the turn-off transistor. This current amounts more

feed is less 5 mA). With a switching threshold of 6 V, the control current of the turn-off transistor is switched off,

that enables the supply voltage to rise up to the limiting voltage. Because the trigger pulse gate, blocked by the

error memory, the oscillation can’t start again.

With error storing and attenuation of the oscillation by overtemperature it can be defined via selection of the

temperature mode, whether the oscillation is automatically triggered after cooling-down of the assembly, or only

after mains disconnection.

Pin Description

Pin 1

TM

Temperature mode selection

As soon as the chip temperature range of 95 °C to 115 °C is reached, the error storage is set. When input TM is

open, the error storing happens only after identification of an overtemperature and a second enquiry, delayed by

one second but showing the same result and causing attenuation of the oscillation.

The multiple enquiry reduces the possibility of coupling in distortions for temperatures in the close neighbourhood

of the temperature switching level.

A new start is only possible after turn-off the mains voltage.

When the input TM is connected to ground, the IC triggers the oscillation again after approximately 10 degrees

decreasing of the chip temperature. Please note, that no enquiry cycle is duty in this mode.

Pin 2

CT

Clock Generator

A clock generator delivers clock pulses of 10 µs pulse width and a repetition frequency of 33 kHz by means of

defined reversing charges of the ramp capacitor connected at pin CT with a nominal value of 82 pF.

All time lapses within the IC are derived from this clock. A variation of capacity of the external capacitor affects all

time responses except the trigger pulse width.

3

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TFA3354