MP4569―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER

MP4569 Rev. 1.0

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13

9/12/2014

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The UVLO threshold can be computed from

below two equations.

TH_Rising

) EN

3M//R2

R1

(1

UVLO

TH_Rising

×

+

=

TH_Falling

) EN

3M//R2

R1

(1

UVLO

TH_Falling

×

+

=

Soft Start Capacitor

The soft start time is the duration when SS is

charged from 0 to FB reference voltage 1V by an

internal 5μA current source. So the capacitor at

SS pin can be chosen according to below

formula:

F)

μ

(

t

C

SS

SS

×

= 5

Feed-Forward Capacitor

As described above that the PWM control

scheme of MP4569 is very special and the

HS_FET turns on when FB drops lower than

reference voltage. This brings good load

transient performance. However, this also makes

the HS_FET turn on moment is very sensitive to

the FB voltage. Once there is noise on FB, the

moment HS_FET turns on is easy to be affected,

and then Fsw jitter would occur. The Fsw jitter is

easy to happen especially when Vo ripple is very

small. To improve the jitter performance, a small

feedforward capacitor between Vo and FB can

be used and typical 39pF is recommended.

PCB Layout

PCB layout is very important to achieve stable

operation. Please follow below guidelines and

use Figure 5 as reference.

1) Keep the path of switching current short and

minimize the loop area formed by input

capacitor, high-side, low-side MOSFET and

output capacitor.

2) Bypass ceramic capacitors should be as

close as possible to the VIN pin.

3) Make sure that all feedback connections are

short and direct. Place the feedback resistors

as close to the chip as possible.

4) Keep SW away from sensitive analog areas

such as FB.

5) For better thermal performance and long-term

reliability consideration, VIN, SW and GND

should be connected to a large copper area

respectively to cool the chip.

Top Layer

Bottom Layer