MP8763 — 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER

MP8763 Rev. 1.3

www.MonolithicPower.com

15

6/21/2016

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Therefore, when driving EN with an external logic

signal, use an EN voltage less than 6V; when

connecting EN to IN through a pull-up resistor or

a resistive voltage divider, select a resistance

that ensures a maximum pull up current less than

1mA.

exceeds 6V, then the minimum resistance for the

IN

UP

DOWN

V

6V

6V

1mA

R

R

−

−

≤

(12)

connected), then the VCC UVLO threshold

value is:

IN

UP

V

6V

R

( )

1mA

−

≥

Ω

(13)

A typical pull-up resistor is 100k .

External VCC bias

An external 5V VCC bias can disable the internal

LDO, in this case, Vin can be as low as 2.5V.

Soft-Start

The MP8763 employs soft-start (SS) to ensure a

smooth output during power-up. When the EN

pin goes HIGH, an internal current source (20µA)

charges the SS capacitor. The SS capacitor

voltage takes over the REF voltage to the PWM

comparator. The output voltage smoothly ramps

up with the SS voltage. It continues ramping up

this point, soft-start finishes and the device

enters steady state operation.

Determine the SS capacitor value as follows:

(

)

(

)

(

)

( )

×

µ

=

SS

SS

SS

REF

T

ms

I

A

C

nF

V

V

(14)

If the output capacitors are large, then avoid

setting a short SS time otherwise it would risk

hitting the current limit during SS.

Pre-Bias Startup

The MP8763 is designed for monotonic startup

for pre-biased loads. If the output is pre-biased to

a certain voltage during startup, the IC will

disable switching for both high-side and low-side

switches until the voltage on the soft-start

capacitor exceeds the sensed output voltage at

the FB pin.

Power Good (PG)

The MP8763 has a power-good (PG) output. The

PG pin is the open drain of a MOSFET. Connect

it to VCC or some other voltage source that

measures less than 5.5V through a pull-up

resistor (typically 100k ). After applying the input

voltage, the MOSFET turns ON so that the PG

pin is pulled to GND before the SS is ready. After

the FB voltage reaches 91% of the REF voltage,

the PG pin is pulled HIGH after a 2.5ms delay.

When the FB voltage drops to 80% of the REF

voltage or exceeds 120% of the nominal REF

voltage, the PG pin is pulled LOW.

If the input supply fails to power the MP8763, the

PG pin is also pulled low even though this pin is

tied to an external DC source through a pull-up

resistor (typically. 100k ).

Over-Current Protection (OCP)

The MP8763 features two current limit levels for

over-current conditions: low-side valley current

limit and low-side negative current limit.

Low-Side Valley Current Limit:

The device

monitors the inductor current during LS-FET

ON state. At the end of LS-FET ON time, the

LS-FET sourcing current is compared to the

internal positive-valley-current limit. If the

valley current limit is less than LS-FET

sourcing current, the HS-FET remains OFF

and LS-FET remains ON. When LS-FET

sourcing current drops below the valley

current limit, the LS-FET turns OFF and the

HS-FET turns ON for a fixed time determined

voltage.

During OCP, the device tries to recover from

the over-current fault with hiccup mode: the

chip

disables

the

output

power

stage,

discharges the soft-start capacitor and then

automatically retries soft-start. If the over-

current condition still holds after soft-start

ends, the device repeats this operation cycle

until the over-current conditions disappear

and then output rises back to regulation level.

OCP offers non-latch protection.