MP4026 – PRIMARY SIDE CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC

MP4026 Rev. 1.1

www.MonolithicPower.com

11

9/9/2015

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Power-Factor Correction

The MULT pin is connected to a pull up resistor

from the rectified-instantaneous-line voltage and

fed as one input of the Multiplier. The multiplier

output is sinusoidal.. This signal provides the

reference for the current comparator and

comparing with the primary-side-inductor current,

which sets the sinusoidal primary-peak current.

This helps to achieve a high-power factor.

Inductor current

Multiplier output

Figure 4: Power-Factor Correction

The maximum voltage of the multiplier output to

the current comparator is clamped at 2V for a

cycle-by-cycle current limit.

VCC Under-Voltage Lockout

(9.3V), the MP4026 stops switching and shuts

down. The operating current is very low under

by the external start up resistor from AC line.

lockout waveform.

9.3V

Vcc

Gate

Swit ching

Pu lses

And Regulates the VCC

Auxiliary Winding Takes Charge

Protection happens

24.9V

Figure 5: VCC Start-Up Waveform

Auto Starter

The MP4026 has an integrated auto starter. The

starter times when the MOSFET is OFF: If ZCD

fails to send out another turn-on signal after

190µs, the starter will automatically send out the

turn-on signal to avoid unnecessary shutdowns

due to missing ZCD detections.

Minimum Off Time

The MP4026 operates with a variable switching

frequency; the frequency changes with the

instantaneous-input-line voltage. To limit the

maximum frequency and get a good EMI

performance, the MP4026 employs an internal,

minimum-off-time limiter—5.5µs.

Leading-Edge Blanking

To avoid premature switching-pulse termination

due to the parasitic capacitances discharging

when the MOSFET turns on at normal operation,

the MP4026 uses an internal-leading edge

blanking (LEB) unit between the CS/ZCD pin and

the current-comparator input. During the blanking

time, the path from the CS/ZCD pin to the current

comparator input is blocked. Figure 6 shows the

leading-edge blanking. The LEB time of primary-

side OCP detection is relatively short, 200ns.

t

V

CS

t

Figure 6: Leading-Edge Blanking

Output Over-Voltage Protection

Output

over-voltage

protection

prevents

component damage during an over-voltage

condition. The auxiliary-winding voltage’s positive

plateau is proportional to the output voltage: the

OVP uses the auxiliary winding voltage instead of

directly monitoring the output voltage. Figure 7

shows the OVP sampling unit. Once the ZCD

voltage exceeds 5.1V at gate turn off interval, the

OVP signal will be triggered and latched, the gate

driver will be turned off and the IC works at

the UVLO which will make the IC shut down, and

the system restarts again.