LTM4650-1 datasheet(25/36 Pages) LINER

25 / 36 page

LTM4636

4636f

For more information www.linear.com/LTM4636

applicaTions inForMaTion

ambient, thus maximum junction temperature. Room

temperature power loss curves are provided in Figures 10

through 12. The printed circuit board is a 1.6mm thick six

layer board with two ounce copper for all layers and one

ouncecopperforthetwoinnerlayers.ThePCBdimensions

are 95mm

× 76mm.

Safety Considerations

TheLTM4636doesnotprovidegalvanicisolationfromVIN

to VOUT. There is no internal fuse. If required, a slow blow

fuse with a rating twice the maximum input current needs

tobeprovidedtoprotecteachunitfromcatastrophicfailure.

The fuse or circuit breaker should be selected to limit the

current to the regulator during overvoltage in case of an

internal top MOSFET fault. If the internal top MOSFET

fails, then turning it off will not resolve the overvoltage,

thus the internal bottom MOSFET will turn on indefinitely

trying to protect the load. Under this fault condition, the

input voltage will source very large currents to ground

throughthefailedinternaltopMOSFETandenabledinternal

bottom MOSFET. This can cause excessive heat and board

damage depending on how much power the input voltage

can deliver to this system. A fuse or circuit breaker can be

used as a secondary fault protector in this situation. The

LTM4636 has the enhanced over temperature protection

discussedearlierandschematicapplicationswillbeshown

at the end of the data sheet.

Layout Checklist/Example

The high integration of the LTM4636 makes the PCB

board layout very simple and easy. However, to optimize

its electrical and thermal performance, some layout

considerations are still necessary.

• Use large PCB copper areas for high current paths,

including VIN, GND and VOUT. It helps to minimize the

PCB conduction loss and thermal stress.

• Place high frequency ceramic input and output

capacitors next to the VIN, GND and VOUT pins to

minimize high frequency noise.

• Place a dedicated power ground layer underneath the

unit.

• To minimize the via conduction loss and reduce module

thermal stress, use multiple vias for interconnection

between top layer and other power layers.

• Do not put vias directly on the pad, unless they are

capped or plated over.

• Place test points on signal pins for testing.

• Use a separated SGND ground copper area for

components connected to signal pins. Connect the

SGND to GND underneath the unit.

• Forparallelmodules,tietheCOMPandVFBpinstogether.

Use an internal layer to closely connect these pins

together.

• RSNUB and CSNUB(2.2Ω and 2200pf) values to dampen

switch ringing.

Figure19givesagoodexampleoftherecommendedlayout.

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