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LTC2312-12

231212fa

For more information www.linear.com/LTC2312-12

applicaTions inForMaTion

Overview

The LTC2312-12 is a low noise, high speed, 12-bit succes-

sive approximation register (SAR) ADC. The LTC2312-12

operates from a single 3V or 5V supply and provides a low

drift (20ppm/°C maximum), internal reference and refer-

ence buffer. The internal reference buffer is automatically

configured with a 2.048V span in low supply range (2.7V

to 3.6V) and with a 4.096V span in the high supply range

(4.75V to 5.25V). The LTC2312-12 samples at a 500ksps

rate and supports a 20MHz serial data read clock. The

LTC2312-12 achieves excellent dynamic performance

(72.7dBSINAD,–84dBTHD)whiledissipatingonly15mW

from a 5V supply up to the 500ksps conversion rate. The

LTC2312-12 outputs the conversion data with no cycle

latency onto the SDO pin. The SDO pin output logic lev-

els are supplied by the dedicated OVDD supply pin which

has a wide supply range (1.71V to 5.25V) allowing the

LTC2312-12 to communicate with 1.8V, 2.5V, 3V or 5V

systems. The LTC2312-12 automatically switches to nap

modefollowingtheconversionprocesstosavepower.The

device also provides a sleep power-down mode through

serial interface control to reduce power dissipation during

long inactive periods.

Serial Interface

The LTC2312-12 communicates with microcontrollers,

DSPs and other external circuitry via a 3-wire interface.

A rising CONV edge starts the conversion process which

is timed via an internal oscillator. Following the conver-

sion process the device automatically switches to nap

mode to save power as shown in Figure 7. This feature

saves considerable power for the LTC2312-12 operating

at lower sampling rates. As shown in Figures 5 and 6, it

is recommended to hold SCK static low or high during

tCONV. Note that CONV must be held high for the entire

minimum conversion time (tCONV). A falling CONV edge

enables SDO and outputs the MSB. Subsequent SCK

falling edges clock out the remaining data as shown in

Figures 5 and 6. Data is serially output MSB first through

LSB last, followed by trailing zeros if further SCK falling

edges are applied.

Serial Data Output (SDO)

The SDO output is always forced into the high imped-

ance state while CONV is high. The falling edge of CONV

enables SDO and also places the sample and hold into

sample mode. The A/D conversion result is shifted out

on the SDO pin as a serial data stream with the MSB first.

The MSB is output on SDO on the falling edge of CONV.

Delay t3 is the data valid access time for the MSB. The

following 11 bits of conversion data are shifted out on

SDO on the falling edge of SCK. Delay t4 is the data valid

access time for output data shifted out on the falling edge

of SCK. There is no data latency. Subsequent falling SCK

edges applied after the LSB is output will output zeros

indefinitely on the SDO pin.

The output swing on the SDO pin is controlled by the

OVDD pin voltage and supports a wide operating range

from 1.71V to 5.25V independent of the VDD pin voltage.

Power Considerations

The LTC2312-12 provides two sets of power supply pins:

theanalog powersupply(VDD)andthedigitalinput/output

interface power supply (OVDD). The flexible OVDD supply

allows the LTC2312-12 to communicate with any digital

logic operating between 1.8V and 5V, including 2.5V and

3.3V systems.

Entering Nap/Sleep Mode

Pulsing CONV two times and holding SCK static places the

LTC2312-12 into nap mode. Pulsing CONV four times and

holding SCK static places the LTC2312-12 into sleep mode.

In sleep mode, all bias circuitry is shut down, including the

internal bandgap and reference buffer, and only leakage

currents remain (0.2µA typical). Because the reference

buffer is externally bypassed with a large capacitor (2.2µF),

the LTC2312-12 requires a significant wait time (1.1ms) to

recharge this capacitance before an accurate conversion

can be made. In contrast, nap mode does not power down

the internal bandgap or reference buffer allowing for a fast

wake-upandaccurateconversionwithinoneconversionclock

cycle. Supply current during nap mode is nominally 2mA.

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