LTC6255 datasheet(13/26 Pages) LINER

13 / 26 page

LTC6261/LTC6262/LTC6263

626123fa

For more information www.linear.com/LTC6261

down resistor of 1k to –2V will allow a ‘true zero’ output

swing. In this case, the output can swing all the way to

the bottom rail while maintaining 50dB of open loop gain.

Since the inputs can go 100mV beyond either rail, the op

amp can easily perform ‘true ground’ sensing.

The maximum output current is a function of total supply

voltage. As the supply voltage to the amplifier increases,

theoutputcurrentcapabilityalsoincreases.Attentionmust

be paid to keep the junction temperature of the IC below

150°C when the output is in continuous short-circuit. The

output of the amplifier has reverse-biased diodes con-

nected to each supply. The output should not be forced

more than 0.5V beyond either supply; otherwise current

will flow through these diodes.

Input Protection and Output Overdrive

To prevent breakdown of the input transistors, the input

stages are protected against a large differential input

voltage by two pairs of back-to-back diodes, D5 to D8. If

the differential input voltage exceeds 1.4V, the current in

these diodes must be limited to less than 10mA. These

amplifiersarenotintendedforopenloopapplicationssuch

as comparators. When the output stage is overdriven,

internal limiting circuitry is activated to improve overdrive

recovery. In some applications, this circuitry may draw as

much as 1mA supply current.

ESD

The LTC6261 family has reverse-biased ESD protection

diodes on all inputs and output as shown in Figure 1.

Supply Voltage Ramping

Fast ramping of the supply voltage can cause a current

glitch in the internal ESD protection circuits. Depending on

the supply inductance, this could result in a supply volt-

age transient that exceeds the maximum rating. A supply

voltage ramp time of greater than 1ms is recommended.

Feedback Components

Care must be taken to ensure that the pole formed by the

feedback resistors and the parasitic capacitance at the

inverting input does not degrade stability. For example, in

a gain of +2 configuration with gain and feedback resis-

tors of 10k, a poorly designed circuit board layout with

parasitic capacitance of 5pF (part +PC board) at the ampli-

fier’s inverting input will cause the amplifier to oscillate

due to a pole formed at 3.2MHz. An additional capacitor

of 4.7pF across the feedback resistor as shown in Figure

2 will eliminate any ringing or oscillation.

Shutdown

The single and dual versions have SHDN pins that can

shut down the amplifier to less than 10µA supply current.

The SHDN pin voltage needs to be within 0.6V of V– for

the amplifier to shut down. During shutdown, the output

is in high impedance state. When left floating, the SHDN

pin is internally pulled up to the positive supply and the

amplifier remains enabled.

10k

4.7pF

CPAR

VOUT

VIN

626123 F02

–

LTC6261

Figure 2.

ApplicAtions inForMAtion

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