データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

Preview PDF HTML

LTC6253 データシート(PDF) 20 Page - Linear Technology

部品番号 LTC6253
部品情報  280MHz, 2.9ns Comparator Family with Rail-to-Rail Inputs and CMOS Outputs
PDF  30 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  LINER [Linear Technology]
ホームページ  http://www.linear.com
Logo LINER - Linear Technology

LTC6253 データシート(HTML) 20 Page - Linear Technology

Back Button LTC6253 Datasheet HTML 16Page - Linear Technology LTC6253 Datasheet HTML 17Page - Linear Technology LTC6253 Datasheet HTML 18Page - Linear Technology LTC6253 Datasheet HTML 19Page - Linear Technology LTC6253 Datasheet HTML 20Page - Linear Technology LTC6253 Datasheet HTML 21Page - Linear Technology LTC6253 Datasheet HTML 22Page - Linear Technology LTC6253 Datasheet HTML 23Page - Linear Technology LTC6253 Datasheet HTML 24Page - Linear Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 20 / 30 page
background image
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
20
6752fc
For more information www.linear.com/LTC6752
applicaTions inForMaTion
Latching
TheinternallatchoftheLTC6752-1/LTC6752-2/LTC6752-3
retains the output state when the LE/HYST pin is taken to
less than 300mV above the negative supply.
Figures 7a to 7e illustrate the latch timing definitions. The
latch setup time is defined as the time for which the input
should be stable before the latch pin is asserted low to
ensure that the correct state will be held at the output. The
latch hold time is the interval after which the latch pin is
asserted in which the input signal must remain stable for
the output to be the correct state at the time latch was
asserted. The latch to output delay (tPL) is the time taken
for the output to return to input control after the latch
pin is released. Latching is disabled if the LE/HYST pin
is left floating. Both outputs of the LTC6752-3 are latch
controlled simultaneously.
6752 F07a
+IN – –IN
t > tSETUP
tPD
Q
LE/HYST
6752 F07d
+IN – –IN
t > tHOLD
tPD
Q
LE/HYST
t > tSETUP
6752 F07e
+IN – –IN
tPL
Q
LE/HYST
6752 F07c
+IN – –IN
t < tHOLD
tPD
Q
LE/HYST
6752 F07b
+IN – –IN
t < tSETUP
Q
LE/HYST
Figure 7a. Input State Change Properly Latched
Figure 7b. Input Change Setup Time Too Short
Figure 7c. Input State Not Held Long Enough.
Wrong Output State Latched
Figure 7d. Short Input Pulse Properly
Captured and Latched
Figure 7e. Latched Output Disabled
Shutdown
The LTC6752-2 and LTC6752-3 have shutdown pins
(SHDN, active low) that can reduce the total supply cur-
rent to a typical value of 580μA for the LTC6752-2 and
650µA for the LTC6752-3 (2.5V supply). When the part is
in shutdown, the outputs are placed in a high-impedance
state,sincePFETandNFEToutputtransistorswhosedrains



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか？  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com