ISL5829

FN6020 Rev 1.00

Page 4 of 13

Feb 2002

Pin Descriptions

PIN NO.

PIN NAME

PIN DESCRIPTION

11, 19, 26

AGND

Analog ground.

13, 24

Analog supply (+2.7V to +3.6V).

28

CLK

Clock input.

27

DGND

Connect to digital ground.

10

Digital supply (+2.7V to +3.6V).

20

FSADJ

Full scale current adjust. Use a resistor to ground to adjust full scale output current. Full scale output

14, 23

NC

Not internally connected. Recommend no connect.

12, 25

ICOMP, QCOMP

Compensation pin for internal bias generation. Each pin should be individually decoupled to AGND with

a 0.1

F capacitor.

1-6, 29-40,

43-48

ID11-ID0, QD11-QD0 Digital data input ports. Bit 11 is most significant bit (MSB) and bit 0 is the least significant bit (LSB).

15, 22

IOUTA, QOUTA

Current outputs of the device. Full scale output current is achieved when all input bits are set to binary 1.

16, 21

IOUTB, QOUTB

Complementary current outputs of the device. Full scale output current is achieved on the complementary

outputs when all input bits are set to binary 0.

17

REFIO

Reference voltage input if Internal reference is disabled. The internal reference is not intended to drive an

external load. Use 0.1

F cap to ground when internal reference is enabled.

18

REFLO

7, 8, 41, 42

NC

No connect (NC). Not internally connected. No termination required, may be used for device migration to

higher resolution DACs.

9

SLEEP