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HIP2103 データシート(PDF) 2 Page - Renesas Technology Corp |
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HIP2103 データシート(HTML) 2 Page - Renesas Technology Corp |
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2 / 21 page ![]() HIP2103, HIP2104 FN8276 Rev 0.00 Page 2 of 21 November 27, 2013 Block Diagram Symbol Glossary 3.3V LDO 1 MSEC DELAY 155C OT 12V LDO 1 MSEC DELAY VDen VDD VCen 1 4V UNDER VOLTAGE 20 US DELAY 20 US DELAY VDD HB SLEEP MODE LEVEL SHIFT 4V UNDER VOLTAGE R S Q HO LO HS VSS VDD VBAT LOGIC BIAS HI LI E P A D 100K 100 100k VCC VBAT Logic prevents shoot-through when LI and HI are both high Active pull-down keeps bridge FET off during UV, OT, or sleep 2104 2103 10 US DELAY Time delay functional block with rising edge prop delay (as indicated by the rising arrow on the input) and minimal falling edge delay. 2104 2103 Optional connections as indicated by part numbers HIP2104 HIP2103 2M 100k 100k Boot FET SEE FIGURES 3 AND 4 FOR SLEEP MODE TIMING DETAILS |
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