PC7447 datasheet(13/66 Pages) ATMEL

13 / 66 page

PC7457/47 [Preliminary]

5345B–HIREL–02/04

The PC7457 provides several I/O voltages to support both compatibility with existing

systems and migration to future systems. The PC7457 core voltage must always be pro-

vided at nominal 1.3V (see Table 3 for actual recommended core voltage). Voltage to

the L3 I/Os and processor interface I/Os are provided through separate sets of supply

pins and may be provided at the voltages shown in Table 4. The input voltage threshold

for each bus is selected by sampling the state of the voltage select pins at the negation

of the signal HRESET. The output voltage will swing from GND to the maximum voltage

applied to the OV

DD or GVDD power pins.

Notes:

1. Not implemented on PC7447.

2. Caution: The input threshold selection must agree with the OVDD/GVDD voltages sup-

plied. See notes in Table 2.

3. If used, pull-down resistors should be less than 250

Ω

4. Applicable to L3 bus interface only. ¬HRESET is the inverse of HRESET.

5. 1.8V I/O mode and 1.5V I/O mode are not supported in N spec at VDD = 1.1V.

Thermal Characteristics

Package Characteristics

Notes:

1. See “Thermal Management Information” on page 15 for more details about thermal management.

2. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) tempera-

ture, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance.

3. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.

4. Per JEDEC JESD51-6 with the board horizontal.

5. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

6. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1) with the calculated case temperature. The actual value of RθJC for the part is less than 0.1°C/W.

Table 4. Input Threshold Voltage Setting

BVSEL

Signal

Processor Bus Input

Threshold is Relative to:

L3VSEL

Signal(1)

L3 Bus Input Threshold

is Relative to:

Notes

1.8V

(2)(3)(5)

¬HRESET

Not available

¬HRESET

1.5V

(2)(4)(5)

HRESET

2.5V

HRESET

2.5V

(2)

2.5V

(2)

Table 5. Package Thermal Characteristics

(1)

Symbol

Characteristic

Value

Unit

PC7447

PC7457

RθJA

(2)(3)

Junction-to-ambient thermal resistance, natural convection

°C/W

RθJMA

(2)(4)

Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board

°C/W

RθJMA

(2)(4)

Junction-to-ambient thermal resistance, 200 ft./min. airflow, single-layer (1s) board

°C/W

RθJMA

(2)(4)

Junction-to-ambient thermal resistance, 200 ft./min. airflow, four-layer (2s2p) board

°C/W

RθJB

(5)

Junction-to-board thermal resistance

°C/W

RθJC

(6)

Junction-to-case thermal resistance

< 0.1

°C/W

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