ISL6563

FN9126 Rev 8.00

Page 13 of 20

Jun 10, 2010

schematic in Figure 6 demonstrates coordination of the

ISL6563 with such a rail; the resistor components are

chosen to enable the ISL6563 as the 12V input exceeds

approximately 9.75V. Additionally, an open-drain or open-

collector device can be used to wire-AND a second (or

multiple) control signal, as shown in Figure 6. To defeat the

threshold-sensitive enable, connect ENLL to VCC directly or

via a pull-up resistor.

The ‘11111’ VID code is reserved as a signal to the controller

that no load is present. The controller is disabled while

receiving this VID code and will subsequently start up upon

receiving any other code.

In summary, for the ISL6563 to operate, the following

conditions need be met: VCC and PVCC must be greater

than their respective POR thresholds, the voltage at ENLL

must be greater than 0.61V, and VID has to be different than

‘11111’. Once all these conditions are met, the controller

immediately initiates a soft start sequence.

SOFT-START

The soft-start function allows the converter to bring up the

output voltage in a controlled fashion, resulting in a linear

ramp-up. Following a delay of 16 PHASE clock cycles (about

70

s) between enabling the chip and the start of the ramp,

the output voltage progresses at a fixed rate of 12.5mV per

16 PHASE clock cycles.

Thus, the soft-start period (not including the 70µs wait) up to

switching frequency (typically 222kHz).

The ISL6563 also has the ability to start up into a pre-charged

output, without causing any unnecessary disturbance. The FB

pin is monitored during soft-start, and should it be higher than

the equivalent internal ramping reference voltage, the output

drives hold both MOSFETs off. Once the internal ramping

reference exceeds the FB pin potential, the output drives are

enabled, allowing the output to ramp from the pre-charged level

to the final level dictated by the DAC setting. Should the output

be pre-charged to a level exceeding the DAC setting, the output

drives are enabled at the end of the soft-start period, leading to

an abrupt correction in the output voltage down to the DAC-set

level.

General Application Design Guide

This design guide is intended to provide a high-level

explanation of the steps necessary to create a multiphase

power converter. It is assumed that the reader is familiar with

many of the basic skills and techniques referenced below. In

addition to this guide, Intersil provides complete reference

designs that include schematics, bills of materials, and

example board layouts for all common microprocessor

applications.

MOSFETs

Given the fixed switching frequency of the ISL6563 and the

integrated output drives, the selection of MOSFETs revolves

closely around the current each MOSFET is required to

conduct, the capability of the devices to dissipate heat, as well

as the characteristics of available heat sinking. Since the

ISL6563 drives the MOSFETs with 5V, the selection of

appropriate MOSFETs should be done by comparing and

voltage.

LOWER MOSFET POWER CALCULATION

Since virtually all of the heat loss in the lower MOSFET is

conduction loss (due to current conducted through the channel

in the lower MOSFET can be found in Equation 10:

the peak-to-peak inductor current, and D is the duty cycle

An additional term can be added to the lower-MOSFET loss

equation to account for additional loss accrued during the

dead time when inductor current is flowing through the

lower-MOSFET body diode. This term is dependent on the

the beginning and the end of the lower-MOSFET conduction

interval, respectively.



---------------------------------

=

(EQ. 9)

FIGURE 7. SOFT-START WAVEFORMS FOR ISL6563-BASED

MULTIPHASE CONVERTER

ENLL (5V/DIV)

GND>

T1

GND>

T2

T3

OUTPUT PRECHARGED

BELOW DAC LEVEL

OUTPUT PRECHARGED

ABOVE DAC LEVEL



2

-------------





1D

–



,

–



12

--------------------------------

+

=

(EQ. 10)

2

-------------

2

---------

+



 t

d1

2

-------------

2

---------

–







+

=

(EQ. 11)