X98021

FN8219 Rev 3.00

Page 6 of 29

March 8, 2006

DATACLK

DATACLK

Pixel Data

FIGURE 2. DATA OUTPUT SETUP AND HOLD TIMING

Programmable

Width and Polarity

Analog

Video In

P

1

P

2

P

3

P

4

P

5

P

6

P

7

P

8

P

0

P

9

D

0

R

HS

OUT

8.5 DATACLK Pipeline Latency

R

P

10

P

11

P

12

D

1

D

2

D

3

HSYNC

IN

The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.

The sampling phase setting determines its relative position to the rest of the AFE’s output signals

DATACLK

t

FIGURE 3. 24 BIT OUTPUT MODE

Programmable

Width and Polarity

Analog

Video In

P

1

P

2

P

3

P

4

P

5

P

6

P

7

P

8

P

0

P

9

HS

OUT

8.5 DATACLK Pipeline Latency

P

10

P

11

P

12

HSYNC

IN

The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.

The sampling phase setting determines its relative position to the rest of the AFE’s output signals

DATACLK

G

G

B

G

R

B

t

FIGURE 4. 24 BIT 4:2:2 OUTPUT MODE (FOR YUV SIGNALS)