K6R1016C1C datasheet(6/11 Pages) SAMSUNG

6 / 11 page

K6R1016C1C-C/C-L, K6R1016C1C-I/C-P

CMOS SRAM

Revision 4.0

- 6 -

September 2001

NOTES(READ CYCLE)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or

VOL levels.

4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to

device.

5. Transition is measured

±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

6. Device is continuously selected with CS=VIL.

7. Address valid prior to coincident with CS transition low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

Valid Data

High-Z

tRC

Address

UB, LB

Data out

tHZ(3,4,5)

tAA

tCO

tBA

tOE

tOLZ

tLZ(4,5)

tOH

tOHZ

tBHZ(3,4,5)

tBLZ(4,5)

tPU

tPD

50%

VCC

Current

ICC

ISB

TIMING WAVEFORM OF WRITE CYCLE(1) (OE =Clock)

Address

UB, LB

Data in

Data out

tWC

tCW(3)

tBW

tWP(2)

tAS(4)

tDH

tDW

tOHZ(6)

High-Z

Valid Data

tAW

tWR(5)

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