SSM4321

Data Sheet

Rev. 0 | Page 20 of 24

TIMING DIAGRAMS, PDM MODE

PDM Mode with Current and Voltage Output

SLOT pin is tied to GND through a 47 kΩ resistor; FSYNC_TDM pin is tied to IOVDD.

I

V

IVI

V

IVI

V

IV

IVI

V

IV

IVIV

IVI

PDM_CLK

FSYNC_TDM

PDM_DATA

Figure 47. PDM Mode with Current and Voltage Output

PDM Mode with Current and PVDD Output

SLOT pin is tied to GND through a 47 kΩ resistor; FSYNC_TDM pin is tied to GND.

I

PVDD

I

PVDD

I

PVDD

I

PVDD

I

PVDD

I

PVDD

I

PVDD

I

PVDD

I

PVDD

I

PVDD

I

PVDD

I

PVDD

I

PDM_CLK

FSYNC_TDM

PDM_DATA

Figure 48. PDM Mode with Current and PVDD Output