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ADAU1361BCPZ-R7 データシート(PDF) 59 Page - Analog Devices

部品番号 ADAU1361BCPZ-R7
部品情報  Audio Codec
PDF  80 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

ADAU1361BCPZ-R7 データシート(HTML) 59 Page - Analog Devices

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Data Sheet
ADAU1361
Rev. D | Page 59 of 80
R17: Converter Control 0, 16,407 (0x4017)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
DAPAIR[1:0]
DAOSR
ADOSR
CONVSR[2:0]
Table 44. Converter Control 0 Register
R18: Converter Control 1, 16,408 (0x4018)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
ADPAIR[1:0]
Table 45. Converter Control 1 Register
Bits
Bit Name
Description
[6:5]
DAPAIR[1:0]
On-chip DAC serial data selection in TDM mode.
Setting
Pair
00
First pair (default)
01
Second pair
10
Third pair
11
Fourth pair
4
DAOSR
DAC oversampling ratio. This bit cannot be set for 64× when CONVSR[2:0] is set to 96 kHz.
0 = 128× (default).
1 = 64×.
3
ADOSR
ADC oversampling ratio. This bit cannot be set for 64× when CONVSR[2:0] is set to 96 kHz.
0 = 128× (default).
1 = 64×.
[2:0]
CONVSR[2:0]
Converter sampling rate. The ADCs and DACs operate at the sampling rate set in this register. The converter rate
selected is a ratio of the base sampling rate, fS. The base sampling rate is determined by the operating frequency
of the core clock. The serial port mirrors the converter sampling rates set in this register.
Setting
Sampling Rate
Base Sampling Rate (fS = 48 kHz)
000
fS
48 kHz, base (default)
001
fS/6
8 kHz
010
fS/4
12 kHz
011
fS/3
16 kHz
100
fS/2
24 kHz
101
fS/1.5
32 kHz
110
fS/0.5
96 kHz
111
Reserved
Bits
Bit Name
Description
[1:0]
ADPAIR[1:0]
On-chip ADC serial data selection in TDM mode.
Setting
Pair
00
First pair (default)
01
Second pair
10
Third pair
11
Fourth pair



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