| データシートサーチシステム |
|
8304AMLF データシート(PDF) 1 Page - Integrated Device Technology |
|
|
|||||||||||||||||||||||||||||
8304AMLF データシート(HTML) 1 Page - Integrated Device Technology |
|
1 / 11 page ![]() Low Skew, 1-to-4 LVCMOS/LVTTL Fanout Buffer 8304 DATA SHEET 8304AMLN - PDN CQ-16-01 - LAST TIME BUY EXPIRES MAY 6, 2017 8304 REVISION H 11/19/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 8304 is a low skew, 1-to-4 Fanout Buffer. The 8304 is characterized at full 3.3V for input (V DD ), and mixed 3.3V and 2.5V for output operating supply modes (V DDO ). Guaranteed output and part-to-part skew characteristics make the 8304 ideal for those clock distribution applications demanding well defined performance and repeatability. FEATURES • Four LVCMOS / LVTTL outputs • LVCMOS / LVTTL clock input • CLK can accept the following input levels: LVCMOS, LVTTL • Maximum output frequency: 200MHz • Additive phase jitter, RMS: 0.173ps (typical) @ 3.3V • Output skew: 45ps (maximum) @ 3.3V • Part-to-part skew: 500ps (maximum) • Small 8 lead SOIC package saves board space • 3.3V input, outputs may be either 3.3V or 2.5V supply modes • 0°C to 70°C ambient operating temperature • Available in lead-free (RoHS 6) compliant package BLOCK DIAGRAM PIN ASSIGNMENT 8304 8-Lead SOIC 3.9mm x 4.9mm, x 1.375mm package body M Package Top View VDDO VDD CLK GND 1 2 3 4 Q3 Q2 Q1 Q0 8 7 6 5 Q0 Q1 Q2 Q3 CLK Pulldown |
同様の部品番号 - 8304AMLF |
|
同様の説明 - 8304AMLF |
|
|
|
リンク URL |
| ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | データシートへのリンク | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |