HMC6832ALP5LE datasheet(19/23 Pages) AD

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Data Sheet

HMC6832

Rev. C | Page 19 of 23

THEORY OF OPERATION

INPUT STAGE

The input stage shown in Figure 45 is flexible. It can be driven

single-ended or differential with LVPECL, LVDS, or CML signals.

If driven single-ended, place a large ac-coupled capacitor between

the undriven input and a nearby GND pin. There are pull-up and

pull-down resistors on each single-ended input to set the nominal

dc voltage to VDD/2. The input is selectable by the input select

pin (IN_SEL), a digital pin that can be set to either GND (INx0)

or VDD (INx1). To select the output termination, use the

configuration pin (CONFIG), a digital pin that can be set to

either GND (LVPECL) or to VDD (LVDS). When left floating,

the CONFIG pin is internally pulled to VDD (LVDS).

LVPECL OUTPUT STAGE

The LVPECL output driver produces up to 0.8 V p-p differential

swing into 100 Ω differential loads. LVPECL drivers are terminated

with off-chip resistors that provide the dc current through the

emitter-follower output stage. If unused, LVPECL outputs can

be left floating. VAC_REF is an output reference voltage capable

of sourcing 2 mA at 1.25 V.

VDD

LVDS

100kΩ

CONFIGURATION

CONTROL

CONFIG

HIGH: LVDS

LOW: LVPECL

LVPECL

IN_SEL

HIGH: IN1

LOW: IN0

VDD

50kΩ

INP1

INN1

100pF

INP0

INN0

Figure 45. Input Stage Block Diagram

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