LTC6953 datasheet(36/56 Pages) AD

部品番号	LTC6953

部品情報	Ultralow Jitter, 4.5GHz Clock Distributor with 11 Outputs and JESD204B Support

PDF	56 Pages

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メーカー	AD [Analog Devices]

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36 / 56 page

LTC6953

Rev 0

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

Figure 25. Outputs after SYSREF Request for the EZSync Standalone Design Example (SRQMD = 1)

Figure 24. Outputs after Synchronization for the EZSync Standalone Design Example (SRQMD = 0)

EZS_SRQ OR SSRQ BIT

ADC DEVICE CLOCKS

(OUT1 AND 3)

ADC SYSREFs

(MUTED OUT0 AND 2)

DAC DEVICE CLOCKS

(OUT8 AND 10)

DAC SYSREFs

(MUTED OUT7 AND 9)

FPGA SYSREF

(MUTED OUT4)

FPGA MANAGEMENT CLOCK

(OUT6)

SYSREF VALID CLOCK EDGE

NOT SYNCHRONIZED, PHASE UNDETERMINED

6953 F24

FPGA DEVICE CLOCK

(OUT5)

INTERNAL ADC SYSREF DIVIDERS

(MUTED OUT0 AND 2)

INTERNAL DAC SYSREF DIVIDERS

(MUTED OUT7 AND 9)

INTERNAL FPGA SYSREF DIVIDER

(MUTED OUT4)

EZS_SRQ OR SSRQ BIT

6953 F25

ADC DEVICE CLOCKS

(OUT1 AND 3)

ADC SYSREFs

(OUT0 AND 2)

DAC DEVICE CLOCKS

(OUT8 AND 10)

DAC SYSREFs

(OUT7 AND 9)

FPGA SYSREF

(OUT4)

FPGA MANAGEMENT CLOCK

(OUT6)

FPGA DEVICE CLOCK

(OUT5)

500MHZ

4000MHZ

125MHZ

100MHZ

LTC6953 データシート(PDF) 36 Page - Analog Devices

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