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AD9528

Data Sheet

Rev. D | Page 2 of 67

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

Conditions ..................................................................................... 4

Supply Current.............................................................................. 4

Power Dissipation......................................................................... 5

Input Characteristics—REFA, REFA, REFB, REFB,

VCXO_IN, VCXO_IN, SYSREF_IN, and SYSREF_IN ........... 6

PLL1 Characteristics .................................................................... 6

VCXO_VT Output Characteristics............................................ 7

PLL2 Characteristics .................................................................... 7

Clock Distribution Output Characteristics............................... 7

Output Timing Alignment Characteristics............................... 8

SYSREF_IN, SYSREF_IN, VCXO_IN, and VCXO_IN Timing

Characteristics .............................................................................. 8

Clock Output Absolute Phase Noise—Dual Loop Mode........ 8

Clock Output Absolute Phase Noise—Single Loop Mode...... 9

Clock Output Absolute Time Jitter .......................................... 10

Clock Output Additive Time Jitter (Buffer Mode) ................ 12

Logic Input Pins—RESET, REF_SEL, and SYSREF_REQ .... 12

Status Output Pins—STATUS0 and STATUS1....................... 12

Serial Control Port—Serial Port Interface (SPI) Mode ......... 13

Serial Control Port—I2C Mode ................................................ 14

Absolute Maximum Ratings.......................................................... 15

Thermal Resistance .................................................................... 15

ESD Caution................................................................................ 15

Pin Configuration and Function Descriptions........................... 16

Typical Performance Characteristics ........................................... 19

Input/Output Termination Recommendations .......................... 22

Typical Application Circuit ........................................................... 23

Terminology .................................................................................... 24

Theory of Operation ...................................................................... 25

Detailed Block Diagram ............................................................ 25

Overview ..................................................................................... 25

Component Blocks—PLL1 ....................................................... 25

Component Blocks—PLL2 ....................................................... 27

Clock Distribution ..................................................................... 29

SYSREF Operation ......................................................................... 32

SYSREF Signal Path.................................................................... 32

SYSREF Generator ..................................................................... 34

Serial Control Port ......................................................................... 35

SPI/I2C Port Selection................................................................ 35

SPI Serial Port Operation .......................................................... 35

I2C Serial Port Operation .......................................................... 38

Device Initialization and Calibration Flowcharts ...................... 41

Power Dissipation and Thermal Considerations ....................... 46

Clock Speed and Driver Mode ................................................. 46

Evaluation of Operating Conditions........................................ 46

Thermally Enhanced Package Mounting Guidelines............ 47

Control Register Map..................................................................... 48

Control Register Map Bit Descriptions ....................................... 52

Serial Control Port Configuration (Register 0x0000 to

Clock Part Family ID (Register 0x0003 to Register 0x0006) 53

SPI Version (Register 0x000B).................................................. 53

Vendor ID (Register 0x000C to Register 0x000D) ................ 53

IO_UPDATE (Register 0x000F)............................................... 53

PLL1 Control (Register 0x0100 to Register 0x010B)............. 54

PLL2 (Register 0x0200 to Register 0x0209)............................ 56

Clock Distribution (Register 0x300 to Register 0x0329) ...... 59

Power-Down Control (Register 0x0500 to

Status Control (Register 0x0505 to Register 0x0509)............ 65

Outline Dimensions ....................................................................... 67

Ordering Guide .......................................................................... 67

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