MON35W42 datasheet(9/60 Pages) SMSC

9 / 60 page

FUNCTIONAL DESCRIPTION

General Description

The MON35W42 provides 7 analog positive

inputs, 3 fan speed monitors, up to 4 sets of fan

PWM

(Pulse

Width

Modulation)

control,

thermal

inputs

from

remote

thermistors

2N3904 transistors or Pentium

® II (Deschutes)

thermal diode outputs, case open detection and

beep function output. When the monitored value

exceed

the

set

limit

value

for

voltage,

temperature, or fan counter, the beep output can

be generated. Once the monitor function on the

chip is enabled, the watch dog machine monitors

each function and stores the values. If the

monitored value exceeds the limit value, the

interrupt status is set to 1and an interrupt can be

generated.

Access Interface

The MON35W42 provides two interfaces for the

microprocessor to read/write internal registers.

ISA interface

The ISA Bus can be used to access the internal

registers of the MON35W42. This uses an Index

registers. The upper address bits of the ISA bus

(bits15:3) must be externally decoded for the

Chip Select (nCS), the recommended address is

290h-297h. The Chip then uses the lower three

ISA address bits (bits 2:0) to decode the Index

and Data Registers. These two I/O registers are

described as following:

Port 295h: Index register.

Port 296h: Data register

The register structure is shown in Figure 1.

MON35W42 データシート(PDF) 9 Page - SMSC Corporation

MON35W42 データシート(HTML) 9 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

データシートダウンロード