Preliminary Technical Data

ADF41513

Rev. PrL | Page 17 of 33

REGISTER 0 (R0) MAP

Frequency changes only occur on a write to Register 0.

Variable Modulus

Register 0, Bit 28 = 0 enables the 25-bit fixed modulus.

Register 0, Bit 28 = 1 enables the variable modulus. See the N

Divider and R Counter section for more information.

INT Value

Register 0, Bits[19:4] set the INT value. See the N Divider and R

Counter section for more information.

DB31

CONTROL

BITS

16-BIT INTEGER VALUE (INT)

RESERVED

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7 DB6

DB5 DB4

DB3

DB2

DB1 DB0

0

V1

0

0

0

0

0

0

0

0

0

0

N1

N2

N3

N4

N5

N6

N7

N8

N9

N10

N11

N12

N13

N14

N15

N16

C3(0)

C4(0)

C2(0) C1(0)

INT REGISTER (R0)

RESERVED

N16

N15 ...

N2

N1

INTEGER WORD

PRESCALER 4/5: 23 ≤ INT ≤ 32771

PRESCALER 8/9: 75 ≤ INT ≤ 65535

0

0

...

0

0

NOT ALLOWED

0

0

...

0

1

NOT ALLOWED

0

0

...

1

0

NOT ALLOWED

0

0

...

1

0

NOT ALLOWED

.

.

...

.

.

.

23

.

.

...

.

.

.

0

0

...

0

0

24

1

1

...

0

1

65,533

1

1

...

1

0

65,534

1

1

...

1

1

65,535

V1 VARIABLE MODULUS

0

25-BIT FIXED MODULUS

VARIABLE MODULUS

1

N4

N3

0

0

0

0

0

0

0

1

.

.

.

.

1

0

1

1

1

1

1

1

N5

0

0

0

1

.

.

1

1

1

1

0

0

...

1

1

0

1

1

Figure 21. Register 0 (R0) Map