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PTPS16632RGET データシート(PDF) 12 Page - Texas Instruments

部品番号 PTPS16632RGET
部品情報  60-V, 6-A Power Limiting eFuse
PDF  30 Pages
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI1 - Texas Instruments

PTPS16632RGET データシート(HTML) 12 Page - Texas Instruments

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VIN
VOUT
PGOOD
IIN
u
u
D(INRUSH)
(IN)
(INRUSH)
P
0.5 V
I
VIN
VOUT
PGOOD
IIN
12
TPS1663
SLVSET9A – SEPTEMBER 2018 – REVISED OCTOBER 2018
www.ti.com
Product Folder Links: TPS1663
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Feature Description (continued)
CdVdT = 100 nF
COUT = 1000 µF
RILIM = 4.02 kΩ
Figure 3. Hot Plug In and Inrush Current Control at 24-V Input
8.3.3.1 Thermal Regulation Loop
The power dissipation during power up can be calculated using Equation 3.
(3)
System designs requiring to charge large output capacitors rapidly or powering up an off board load may result in
a higher PD(INRUSH) within the device causing the junction temperature to rise. Once the junction temperature
rises to T(J_REG) level, the device starts regulating the junction temperature at T(J_REG) by controlling the inrush
current profile through the device for a maximum duration of t(Treg_timeout). If the output does not charge up within
this time then the internal FET is turned OFF. Subsequent operation of the device depends on the MODE
configuration (Auto-Retry or latch OFF). This scheme ensures fast and reliable power up operation. Figure 4
illustrates performance of the device operating in thermal regulation loop during charging of a large output
capacitor.
The Thermal regulation loop gets disabled internally after the power up when the internal FET gets fully
enhanced or when the t(Treg_timeout) time is elapsed.
CdVdT = Open
COUT = 10 mF
RILIM = 4.02 kΩ
Figure 4. Thermal Regulation Loop Response During Power up with Large Capacitive Load



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