IXYS

3

IXS839 / IXS839A / IXS839B

Pin Description and Configurations

IXS839

IXS839A

IXS839B

Name

Description

1

3

10

BST

Upper Gate Driver Floating DC Power Terminal for Bootstrap

Capacitor Connection.

2

5

2

PWM

TTL-level Input Signal with active pull-down. PWM input to the

Gate Drivers.

3

7

4

DLY

Terminal for External Delay Capacitor Connection. Capacitor

to Ground at this pin adds propagation delay from Lower Gate

Driver going Low to the Upper Gate Driver going High.

4

8

5

VDD

Positive Supply Terminal for Logic and Lower Gate Driver. A

ceramic bypass capacitor of 1uF should be connected from

VDD to PGND.

5

9

6

LGD

Lower Gate Driver Output Terminal

6

10

7

PGND

Lower Gate Driver DC Power Return Terminal, Logic and

Analog Ground

7

1

8

SW

Upper Gate Driver Floating DC Power Return Terminal

8

2

9

HGD

Upper Gate Driver Output Terminal

N/A

4

1

__

SD

TTL-level Shut Down Input Signal with active pull-up.

SD

N/A

6

3

___

LSD

TTL-level Low Side Shut Down Input Signal with active pull-

up. LSD, when low forces the Lower Gate Driver output low.

When LSD is high, the lower Gate Driver output is enabled.

SOIC and QFN Top View Pin Configurations

HGD

PGND

8

7

6

5

1

2

3

4

SW

LGD

BST

PWM

DLY

VDD

IXS839S1

PWM

1

2

3

4

5

6

7

8

9

10

SD

LSD

DLY

VDD

BST

HGD

SW

PGND

LGD

IXS839BQ2

PWM

1

2

3

4

5

6

7

8

9

10

DLY

VDD

BST

HGD

SW

PGND

LGD

IXS839AQ2

SD

LSD