DLP4710AFQL datasheet(18/43 Pages) TI1

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Tester Channel

Output Under Test

Data Sheet Timing Reference Point

Device Pin

Stop

Start

LS_CLK

LS_WDATA

LS_RDATA

Acknowledge

tPD

VIH

Δ VT

VT+

VT-

VIL

LS_WDATA

LS_CLK

Not to Scale

DLP4710

DLPS125 – NOVEMBER 2018

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Product Folder Links: DLP4710

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(1)

Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.

Figure 11. LPSDR Input Hysteresis

Figure 12. LPSDR Read Out

See Timing for more information.

Figure 13. Test Load Circuit for Output Propagation Measurement

6.8 Switching Characteristics

(1)

Over operating free-air temperature range (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tPD

Output propagation, Clock to Q, rising

edge of LS_CLK input to LS_RDATA

output. Figure 12

CL = 45 pF

Slew rate, LS_RDATA

0.5

V/ns

Output duty cycle distortion, LS_RDATA

40%

60%

DLP4710AFQL データシート(PDF) 18 Page - Texas Instruments

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