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Rev. 1.0
3
PIN DESCRIPTIONS
Name
Type
Function
A0 – A12
Input
Address inputs for selecting one of the 8,192 x 8 bit words in the RAM
/CE1,CE2
Input
/CE1 is active LOW and CE2 is active HIGH. Both chip enables must be
active when data read from or write to the device. If either chip enable is not
active, the device is deselected and in a standby power down mode. The DQ
pins will be in high impedance state when the device is deselected.
/WE
Input
The Write enable input is active LOW. It controls read and write operations.
With the chip selected, when /WE is HIGH and /OE is LOW, output data will
be present on the DQ pins, when /WE is LOW, the data present on the DQ
pins will be written into the selected memory location.
/OE
Input
The output enable input is active LOW. If the output enable is active while the
chip is selected and the write enable is inactive, data will be present on the
DQ pins and they will be enabled. The DQ pins will be in the high impedance
state when /OE is inactive.
DQ0~DQ7
I/O
These 8 bi-directional ports are used to read data from or write data into the
RAM.
Vcc
Power
Power Supply
Gnd
Power
Ground
NC
No connection
TRUTH TABLE
MODE
/CE1
CE2
/WE
/OE
DQ0~7
Vcc Current
H
X
X
X
Standby
X
L
X
X
High Z
ICCSB, ICCSB1
Output
Disable
L
H
H
H
High Z
ICC
Read
L
H
H
L
DOUT
ICC
Write
L
H
L
X
DIN
ICC
High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
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