7 / 8 page
SPT
7
9/8/98
SPT7870
Notes:
1)
= Line termination.
2)
* = 0.01 µF chip capacitor in parallel with 2.2 µF Tantalum capacitor.
3) Immediate output buffer is highly recommended to optimize the
performance due to reflection.
+A5
-A5.2
CLK
CLK
VB
VT
VM
VIN
MINV LINV
+A5
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
AGND VEE
VCC
D10
DGND
-D2 V
50
Ω
.01
FB1
-D5.2
Analog
Input
ECL
Differential
Clock Input
.01
.01
Interfacing
Logic
SPT7870
*
+5 V
-5.2 V
AGND
+A5
-A5.2
+
10 µF
+
10 µF
-2 V
-5.2 V
DGND
-D2
-D5.2
+
10 µF
+
10 µF
*
Figure 4 - SPT7870 Digital Outputs
Equivalent Circuit
Figure 2 - Typical Interface Circuit
Figure 3 - SPT7870 Clock Input Equivalent
Circuit
AGND
DGND
(ESD)
(ESD)
ECL/PECL
OUT
VEE
AGND
CLK
26 k
Ω
AVCC
VEE
6 k
Ω
52 k
Ω
-1.3 V
(ESD)
(ESD)
NCLK
26 k
Ω
(ESD)
(ESD)
PACKAGE OUTLINE
44L Cerquad
C
D
A
B
A
B
0 - 5°
E
F
G
H
1
44
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.550 typ
13.97 typ
B
0.685
0.709
17.40
18.00
C
0.037
0.041
0.94
1.04
D
0.016 typ
0.41 typ
E
0.008 typ
0.20 typ
F
0.027
0.051
0.69
1.30
G
0.006 typ
0.15 typ
H
0.080
0.150
2.03
3.81
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