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TIMING DIAGRAMS
FIGURE 24 – EXTERNAL PROGRAM MEMORY READ CYCLE
A0 - A7
INSTR. IN
A8 - A15
ALE
nPSEN
PORT 0
PORT 2
t11
t10
t2
t1
t6
t7
t3
t8
t5
t4
t9
Parameter
min
typ
max
units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
ALE Pulse Width
Address Valid to ALE Low
ALE Low to nPSEN Low
nPSEN Low to Valid Instruction Input
nPSEN Low to Address Float
Address to Valid Instruction Input
Address Hold after ALE
ALE Low to Valid Instruction Input
nPSEN Pulse Width
Input Instruction Hold after nPSEN
Input Instruction Float after nPSEN
85
7
22.6
27
142.5
0
82.5
10
207.5
150
37.5
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
AC CHARACTERISTICS (0°C - 70°C, 5.0V ± 10%)
100 pF Loading for ALE, PORT0, and nPSEN; 16 MHz Processor Clock
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