GaN Power Transistors

DT12030P

GaN Power Transistors

DT12030P

Characteristics

Conditions

Symbol

Min

Typ

Max

Unit

DC Characteristics

*1

V

=

Gate Threshold Voltage

10V

7.2mA

-3.8

50V

-3.0

-2.3

100mA

Gate Quiescent Voltage

50V

-

-

-2.6

D

V

=

100mA

Saturated Drain Current

*2

6V

A

2V

-

5.8

7.0

Saturated Drain Current

V

Drain-Source Breakdown Voltage

-8V

DS

2V

150

-

-

V

7.2mA

Drain-Source Breakdown Voltage

150

-

-

V

=

Gate Leakage Current

-8V

-1.6

-

-

mA

120V

mA

120V

-

Drain Leakage Current

-8V

2.9

-

V

=

120V

RF Characteristics (Fc=2595MHz unless otherwise noted)

50V

Saturated Output Power

*3,6

50V

30

100mA

-

-

W

DQ

I

=

100mA

100mA

Pulsed Drain Efficiency

*3

%

50V

-

η

70

75

P

100mA

Pulsed Drain Efficiency

*3

%

-

η

70

75

Modulated Gain

*4

50V

18.0

-

dB

100mA

17.0

P

V

=

Modulated Gain

*4

18.0

-

dB

100mA

38.5dBm

17.0

-25.0

LTE Linearity

*4

50V

ACLR

-30.0

dBc

-

P

V

= 50V

100mA

38.5dBm

-25.0

LTE Linearity

ACLR

-30.0

dBc

-

30.0

35.0

-

%

Modulated Drain Efficiency

*4

50V

η

P

100mA

38.5dBm

30.0

35.0

-

%

Modulated Drain Efficiency

η

50V

Output Mismatch Stress

*3, 5

50V

VSWR

-

-

10:1

ψ

100mA

P

Note

Note

*1 Measured on wafer prior to packaging.

*2 Scaled from PCM data.

*2 Scaled from PCM data.

*3 Pulse width 100μsec, Duty Cycle 10%.

*4 Measured in the DT12030P test board amplifier circuit, under LTE 10MHz, PAR7.5dB @0.01% probability on CCDF.

*4 Measured in the DT12030P test board amplifier circuit, under LTE 10MHz, PAR7.5dB @0.01% probability on CCDF.

*5 Measured in the DT12030P test board amplifier circuit. No damage at all phase angles.

*6 Psat is defined as ΔPout/ΔPin<0.1, where ΔPin is increased input power, ΔPout is increased output power.

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36 / rfsales@rfhic.com

US Facility : 919-677-8780 / sales@rfhicusa.com

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All specifications may change without notice

Version 1.0