¡ Semiconductor

MSM6691

5

PIN DESCRIPTIONS

Symbol

Type

Description

I

Power

GND

I

GND

XT

I

Oscillator

XT

O

Oscillator

TEST

I

IC test. Set to "L".

TEST

I

IC test. Set to "H".

SAD

I

Initial address of R/W

SAS

I

Clock to input serial address data to internal register

TAS

I

Load serial data, input to address register, and reset to internal address counter.

RWCK

I

Clock to read and write data register information. At RWCK fall, internal operation

starts. In read mode data input to XDIN is latched and output the DOUT terminal.

In write mode, DIN (D I/O) output data MSM6388 (MSM6588) is input to the DIN

pin of DRAM. At RWCK the fall internal address counter automatically increments,

WE

I

Select R/W modes

XWE

O

Control DRAM

A0 to A10

O

Address control DRAM

RAS

O

Control DRAM

CAS1

O

Control DRAM

CAS2

CAS3

CAS4

XDIN

I

Write data

DOUT

O

Chip select when 1-M DRAM is connected.

Because input terminal to select most significant address when 4-M DRAM is

connected.

CS1

CS2

CS3

CS4

BANK0

BANK1

4M/1M

I

I

I

Select 4-M DRAM or 1-M DRAM for connection.

"L" 1M DRAM connected; 4-M DRAM connected

Chip select data when 4-M DRAM is connedted.

Terminal is used to select desired DRAM from DRAMs connected to select terminals.

CAS1 to CAS4. Set to "L" when 1-M DRAM is connected.

BKLE

I

Latch data, input to BANK0, BANK1, when 4-M DRAM is used. "L" indicates a

"through" setting. "H" indicates a "latch" setting. Set to "L" when 1-M DRAM is used.

Select Terminal

Bank1

Bank0

CAS1

LL

CAS2

LH

CAS3

HL

CAS4

HH

Read data