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M65818AFP データシート(PDF) 29 Page - Renesas Technology Corp

部品番号 M65818AFP
部品情報  Digital Amplifier Processor of S-Master Technology
PDF  39 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M65818AFP データシート(HTML) 29 Page - Renesas Technology Corp

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M65818AFP
Rev.1.00, Sep.04.2003, page 29 of 38
Table 6-2-4 Fs Selection for De-emphasis filter (De-emphasis is "ON" except for bit9=L and bit10=L)
bit
Flag Name
32.0K
44.1K
48.0K
OFF
9EMPFS1
H
L
H
L
10
EMPFS2
H
H
L
L
Table 6-2-5 Selection of PWM Output form
bit
Flag Name
PWM Output
Form
PWM Output
Form
PWM Output
Form
PWM Output Form
22
PWMMODE0
L
H
L
H
23
PWMMODE1
L
L
H
H
*Output Form 2 is available only under following conditions.
MCKSEL="L" (Secondary Side Master Clock 1024fso) , Serial Control System2 mode,
bit17(
NSOBIT) = "H" (5bit), bit16( NSSPEED) = "L" (16fso).
In case of the setting and release for PWM Output Form 2,
Refer to "The NOTE1 at setting PWM output Form 2" on next page.
• Selection of Input format (bit3,bit4:IFMT0,IFMT1)
Refer to Table 6-2-1
Selection of Input format function is available only condition of `Normal` mode.
Otherwise, Selection of Input format function is unavailable under conditions of `External 8fs Input`
and `SACD Input` modes (Interlocked with MODE1 and MODE2 pins).
Detail setting of `External 8fs Input` and `SACD` modes are shown in Chapter 5-4 and 5-5.
• Setting of Input Word Length (bit5,bit6:IBIT0,IBIT1).
Refer to Table 6-2-
2.
Setting of Input Data Word Length is available only MSB First Right Justified.
• Selection of Input Sampling Rate (bit7,bit8:ISF0,ISF1).
Refer to Table 6-2-
3.
• Fs Selection for De-emphasis Filter on/off (bit9, bit10 : EMPFS1, EMPFS2).
Refer to Table 6-2-
4.
(bit9,bit10):
("L","L")…
De-emphasis Filter is "off".
except ("L","L")… De-emphasis Filter on (Fs setting).
• Zero Mute at data input (bit11: DF1IMUTE).
DF1IMUTE :
"L"…Mute release.
"H"…Mute.
The input data from DATA pin under normal mode is muted in this setting.
• Zero Mute at Sampling Rate Converter Input (bi12: DF2IMUTE).
DF2IMUTE :
"L"…Mute release.
"H"…Mute.
DF2IMUTE is available for sampling rate converter input data.
DF2IMUTE executes zero mute of input data from DATA pin under condition of `Normal` mode and
from DSDL/DSDR pins under condition of `SACD-fsi ` mode.



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