
1:10 Clock Fanout Buffer
COMLINK™ SERIES
CY2CC910
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07348 Rev. *A
Revised October 3, 2002
Features
• Low-voltage operation
• Full-range support:
— 3.3V
— 2.5V
— 1.8V
• Over voltage tolerant input hot swappable
• 1:10 fanout
• Drives either a 50-Ohm or 75-Ohm load
• Low-input capacitance
• Low-output skew
• Low-propagation delay
• Typical (tpd < 4 ns)
• High-speed operation:
— -200 MHz@1.8V
— 650 MHz@2.5V/3.3V
• Industrial versions available
• Available packages include: SOIC, SSOP
Description
The Cypress series of network circuits are produced using
advanced 0.35 micron CMOS technology, achieving the indus-
tries fastest logic and buffers.
The Cypress CY2CC910 fanout buffer features one input and
ten outputs. Ideal for conversion from/to 3.3V/2.5V/1.8V
Designed for Data Communications clock management appli-
cations, the large fanout from a single input reduces loading
on the input clock.
Cypress employs unique AVCMOS type outputs VOI™
(Variable Output Impedance) that dynamically adjust for
variable impedance matching and eliminate the need for
series damping resistors and reduce noise overall.
Pin Description
Pin Number
Pin Name
Description
1
IN
Input
2,6,10,13,17
GND
Ground
4,8,15,20
VDD
Power Supply
3,5,7,9,11,12,14,16,18,19
Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10
Output
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
20 pin SOIC/SSOP
VDD
Q10
Q9
GND
Q8
VDD
Q7
GND
Q6
Q5
IN
GND
Q1
VDD
Q2
GND
Q3
VDD
Q4
GND
OUTPUT
(AVCMOS)
IN
3
11
14
12
9
7
5
16
18
19
Q1
Q5
Q7
Q6
Q4
Q3
Q2
Q8
Q9
Q1 0
GN D
VD D
INPUT
(AVCMOS)
2,6,10
13,17
4,8
15,20
1
Block Diagram
Pin Configuration