DS1232LP/LPS

Low Power MicroMonitor Chip

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2

OPERATION – POWER MONITOR

The DS1232LP/LPS detects out-of-tolerance power supply conditions and warns a processor-based system of impending power

failure. When Vcc falls below a preset level as defined by TOL, the Vcc comparator outputs the signals RST and

. When TOL is

connected to ground, the RST and

signals become active as Vcc falls below 4.75 volts. When TOL is connected to Vcc, the RST

and

signals become active as Vcc falls below 4.5 volts. The RST and

are excellent control signals for a microprocessor, as

processing is stopped at the last possible moments of valid Vcc. On power-up, RST and

are kept active for a minimum of 250 ms

to allow the power supply and processor to stabilize.

OPERATION – PUSHBUTTON RESET

The DS1232LP/LPS provides an input pin for direct connection to a pushbutton (Figure 1). The pushbutton reset input requires an

active low signal. Internally, this input is debounced and timed such that RST and

signals of at least 250ms minimum are

generated. The 250ms delay starts as the pushbutton reset input is released from low level.

OPERATION – WATCHDOG TIMER

The watchdog timer function forces RST and

signals to the active state when the

input is not stimulated for a predetermined

time period. The time period is set by the TD input to be typically 150ms with TD connected to ground, 600 ms with TD left

unconnected, and 1.2 seconds with TD connected to Vcc. The watchdog timer starts timing out from the set time period as soon as

RST and

are inactive. If a high-to-low transition occurs on the

input pin prior to timeout, the watchdog timer is reset and

begins to timeout again. If the watchdog timer is allowed to timeout, then the RST and

signals are driven to the active state for

250ms minimum. The

input can derived from microprocessor address signals, data signals, and/or control signals. When the

microprocessor is functioning normally, these signals would, as a matter of routine, cause the watchdog to be reset prior to timeout. To

guarantee that the watchdog timer does not timeout, a high-to-low transition must occur at or less than the minimum shown in Table 1.

A typical circuit example is shown in Figure 2.

MICROMONITIOR BLOCK DIAGRAM