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High Speed CMOS Logic – 54HC112

Dual J-K Flip-Flops with preset and clear; negative edge trigger in bare die form

Rev 1.0

24/11/17

Output Drive Capability: 10 LSTTL Loads

Bus Drive Capability: 15 LSTTL Loads

Low Input Current: 1µA

Outputs directly interface CMOS, NMOS and TTL

Operating Voltage Range: 2V to 6V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Die Size (Unsawn)

1500 x 1700

59 x 67

µm

mils

Minimum Bond Pad Size

120 x 120

4.72 x 4.72

µm

mils

Die Thickness

350 (±20)

13.78 (±0.79)

µm

mils

Top Metal Composition

Al 1%Si 1.1µm

Back Metal Composition

N/A – Bare Si

CMOS High Noise Immunity

Function compatible with 54LS112

Full Military Temperature Range.

Features:

Ordering Information

The 54HC112 is fabricated using a 2.5µm 5V CMOS

process and has the same high speed performance of

LSTTL combined with CMOS low power consumption.

Each flip-flop has independent J, K, preset, clear, clock

inputs and Q Q outputs. A high level at the clock input

enables the J and K inputs to accept data. The device

changes state on the negative going transition of the clock

pulse. Preset and clear are independent of the clock and

are accomplished by a low logic level on the corresponding

input. Schmitt-trigger action in the clock input makes the

The following part suffixes apply:

Description

Die Dimensions in µm (mils)

1500 (59)

No suffix - MIL-STD-883 /2010B Visual Inspection

“H” - MIL-STD-883 /2010B Visual Inspection

+ MIL-PRF-38534 Class H LAT

“K” - MIL-STD-883 /2010A Visual Inspection (Space)

+ MIL-PRF-38534 Class K LAT

LAT = Lot Acceptance Test.

For further information on LAT process flows see below.

www.siliconsupplies.com\quality\bare-die-lot-qualification

Supply Formats:

Mechanical Specification

Default – Die in Waffle Pack (100 per tray capacity)

Sawn Wafer on Tape – On request

Unsawn Wafer – On request

Die Thickness <> 350µm(14 Mils) – On request

Assembled into Ceramic Package – On request

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