GD25B127DSFS datasheet(22/65 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25B127D

7.11.

Quad I/O Fast Read (EBH)

The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the

3-byte address (A23-

0) and a “Continuous Read Mode” byte and 4-dummy clock4-bit per clock by IO0, IO1, IO2, IO3, and

each bit is latched in on the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0,

IO1, IO2, IO3. The command sequence is shown in followed Figure13. The first byte addressed can be at any location. The

address is automatically incremented to the next higher address after each byte of data is shifted out.

Quad I/O Fast Read with

“Continuous Read Mode”

The

Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous Read

Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next

Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH command code. The

command sequence is shown in followed Figure13a

. If the “Continuous Read Mode” bits (M5-4) do not equal to (1, 0), the

next command requires the command code, thus returning to

normal operation. A “Continuous Read Mode” Reset command

can be used to reset (M5-4) before issuing normal command.

Figure13. Quad I/O Fast Read Sequence Diagram (M5-4

≠(1, 0))

Command

EBH

CS#

SCLK

SI(IO0)

SO(IO1)

9 10 11 12 13 14 15

16 17 18 19 20 21 22 23

A23-16 A15-8 A7-0

M7-0

IO2

IO3

Dummy

Byte1 Byte2

Figure13a. Quad I/O Fast Read Sequence Diagram (M5-4= (1, 0))

CS#

SCLK

9 10 11 12 13 14 15

SI(IO0)

SO(IO1)

IO2

IO3

A23-16 A15-8 A7-0

M7-0

Dummy

Byte1 Byte2

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