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GD25LE16CLIGR データシート(PDF) 35 Page - GigaDevice Semiconductor (Beijing) Inc.

部品番号 GD25LE16CLIGR
部品情報  1.8V Uniform Sector Dual and Quad Serial Flash
PDF  67 Pages
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メーカー  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
ホームページ  http://www.gigadevice.com/
Logo GIGADEVICE - GigaDevice Semiconductor (Beijing) Inc.

GD25LE16CLIGR データシート(HTML) 35 Page - GigaDevice Semiconductor (Beijing) Inc.

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1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LE16C
35
Figure32. Program Security Registers command Sequence Diagram
7.31 Read Security Registers (48H)
The Read Security Registers command is similar to Fast Read command. The command is followed by a 3-byte address
(A23-A0) and a dummy byte, and each bit is latched-in on the rising edge of SCLK. Then the memory content, at that
address, is shifted out on SO, and each bit is shifted out, at a Max frequency fC, on the falling edge of SCLK. The first byte
addressed can be at any location. The address is automatically incremented to the next higher address after each byte of
data is shifted out. Once the A8-A0 address reaches the last byte of the register (Byte 1FFH), it will reset to 000H, the
command is completed by driving CS# high.
Address
A23-16
A15-12
A11-9
A8-0
Security Register #1
00H
0 0 0 1
0 0 0
Byte Address
Security Register #2
00H
0 0 1 0
0 0 0
Byte Address
Security Register #3
00H
0 0 1 1
0 0 0
Byte Address
Figure33. Read Security Registers command Sequence Diagram
Command
0
1
2
3
4
5
6
7
48H
CS#
SCLK
SI
SO
High-Z
8
9 10
28 29 30 31
3
2
1
0
23 22 21
24-bit address
MSB
34 35 36 37
33
6
5
4
3
2
1
0
38 39
Data Out1
32
42 43 44 45
41
46 47
40
7
6
5
4
3
2
1
0
7
6
5
7
Data Out2
CS#
SCLK
SI
SO
MSB
Dummy Byte
Command
0
1
2
3
4
5
6
7
42H
CS#
SCLK
SI
8
9 10
28 29 30 31
3
2
1
0
23 22 21
24-bit address
42 43 44 45
41
46 47
40
50 51 52 53
49
54 55
48
6
5
4
3
2
1
0
7
CS#
SCLK
SI
MSB
Data Byte 2
32 33 34 35
7
6
5
4
3
2
1
0
MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
Data Byte 1
Data Byte 3
Data Byte 256
MSB
MSB
MSB
36 37 38 39



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