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GD25LE80CSJG データシート(PDF) 55 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25LE80CSJG データシート(HTML) 55 Page - GigaDevice Semiconductor (Beijing) Inc. |
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55 / 68 page ![]() 1.8V Uniform Sector Dual and Quad Serial Flash GD25LE80C 55 Figure 41. Serial Input Timing SCLK CS# SI MSB SO High-Z LSB tCHSL tSLCH tDVCH tCHDX tSHCH tCHSH tCHCL tCLCH tSHSL Figure 42. Output Timing Figure 43. Resume to Suspend Timing CS# Resume Command tRS Suspend Command Figure 44. Hold Timing CS# SCLK SO SI Least significant address bit (LIB) in tCLQV tCLQX tCLQX tCLQV tCLH tCLL tSHQZ LSB CS# SCLK SO HOLD# tCHHL tHLQZ tHLCH tCHHH tHHCH tHHQX SI do not care during HOLD operation. |
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