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GD25LE256DFEG データシート(PDF) 28 Page - GigaDevice Semiconductor (Beijing) Inc.

部品番号 GD25LE256DFEG
部品情報  1.8V Uniform Sector Dual and Quad Serial Flash
PDF  83 Pages
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メーカー  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
ホームページ  http://www.gigadevice.com/
Logo GIGADEVICE - GigaDevice Semiconductor (Beijing) Inc.

GD25LE256DFEG データシート(HTML) 28 Page - GigaDevice Semiconductor (Beijing) Inc.

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1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LE256D
28
7.10. Dual Output Fast Read (3BH)
The Dual Output Fast Read command is followed by 3-byte address (A23-A0) or a 4-byte address (A31-A0) and a
dummy byte, and each bit is latched in on the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock
cycle from SI and SO. The command sequence is shown in followed Figure11. The first byte addressed can be at any
location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The
default read mode is 3-byte address mode, and the lower 128Mbit can be read with a single Dual Output Fast Read (3BH)
command. By entering 4-byte address mode, or to set EN4B (S11) bit to 1, the higher 128Mbit can be read with a single
Dual Output Fast Read (3BH) command.
Figure11. Dual Output Fast Read Sequence Diagram
Command
0
1
2
3
4
5
6
7
3BH
CS#
SCLK
SI
SO
High-Z
8
9 10
28 29 30 31
3
2
1
0
23 22 21
24-bit address
MSB
34 35 36 37
33
5
3
1
7
5
3
1
38 39
Data Out1
32
42 43 44 45
41
46 47
40
7
Data Out2
CS#
SCLK
SI
SO
MSB
Dummy Clocks
4
2
0
6
4
2
0
6
6
7
Note: The device default is in 24-bit address mode. For 4-byte mode, the address length becomes 32-bit.



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