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MT7697 データシート(PDF) 26 Page - List of Unclassifed Manufacturers |
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MT7697 データシート(HTML) 26 Page - List of Unclassifed Manufacturers |
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26 / 81 page ![]() MT7697 Internet-of-Things Wireless Connectivity © 2016 MediaTek Inc. Page 26 of 81 This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s). Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited. Table 2-12. General Purpose Timer Types Mode Clock speed Interrupt Source GPT0 Interrupt-based 1KHz or 32KHz GPT GPT1 Interrupt-based 1KHz or 32KHz GPT2 Free-run 1KHz or 32KHz n/a GPT3 Interrupt based 26MHz (oscillator clock) GPT3 GPT4 Free-run Bus clock or bus clock / 2 n/a 2.4.7 Watchdog Timer MT7697 features the watchdog timer for CM4, which is used to recover the system to the initial status when the system hangs due to some malfunction. WDT provides two ways to generate the WDT event: Triggered by the time-out event (by configuring WDT_MODE:0x83080030 and WDT_LENGTH:0x83080034). The WDT has an 11-bit counter and it uses the 32 KHz clock. The software regularly restarts the timer to prevent it from expiring. If it fails to restart the WDT, the timer would expire and generate a WDT event. Triggered by software programming (WDT_SWRST:0x83080044). WDT provides the following options when a WDT event is generated: 0x83080030[3]=0: Reset mode - 0x8300917C[16] = 1: WDT whole chip mode. Reset the whole chip including CM4 and N9 subsystems. - 0x8300917C[16] = 0: WDT MCU mode. Reset CM4 subsystem only. 0x83080030[3]=1: Interrupt mode -Issue an interrupt to CM4 instead of resetting whole chip or CM4 subsystem. The WDT module can only be reset by the external reset (SYS_RST_N) and the PMU reset. Some WDT control registers feature a key protection mechanism such that an unintentional access would be prevented. WDT also provides the capability for CM4 software to interrupt N9 or reset N9 (by configuring WDT_DUAL_CORE:0x83080080). |
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